?2000 california micro devices corp. all rights reserved. 2/00 1 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices PACGTL high performance gtl termination network for socket 370 processors features ? 24 terminations in a single package ? 5 chip solution for all 119 gtl terminations ? high speed termination network ? center ground pin placement reduces ground bounce and eases board layout ? very low cross-talk ? saves board space and reduces assembly cost applications ? high performance servers ? high performance desk top systems ? intel celeron? and pentium? cpus c0290498d all trademarks are the property of their respective holders. p/active ? is a registered trademark and pac? is a trademark of california micro devices. application information high speed microprocessors demand unique, high speed bus termination. the PACGTL termination network provides 24 terminations per package and meets the requirements for high speed terminations. the termination resistor values are 56 or 120 ohms each. five devices provide the necessary terminations for the 32-bit address bus, 64-bit data bus, and the control of status signals. potential board layout solutions are included in this datasheet. this termination network provides high performance, high reliability, and low cost through manufacturing efficiency. the termination resistor elements are fabricated using state-of-the-art thin film manufacturing. this integrated solution is silic on- based and has the same reliability characteristics of today?s microprocessor products. the thin film resistors have very high stability over temperature, over applied voltage, and over life. in addition, the qsop (ssop) industry standard packaging is easy to handle in manufacturing and yields high reliability similar to other semiconductor components. * pac560gtl or p ac121gtl used as a terminator. signal on a single victim line when all other lines are driven synchronously and simultaneously. s e u l a v d r a d n a t s ) r ( r o t s i s e rs m h o 0 2 1 r o 6 5 ) r ( e c n a r e l o t e t u l o s b a+ % 5 r c t+ m p p 0 5 1 e g n a r e r u t a r e p m e t g n i t a r e p oc 0 7 o t c 0 ) c 0 7 ( g n i t a r r e w o p e g a k c a p x a mw 0 0 . 1 e c n a t s i s e r n o i t a l u s n i m u m i n i mg e m 0 0 0 , 0 1 w * k l a t - s s o r c% 4 ( r w ) e d o c / g n i t a r r e w o p r o t s i s e r 6 50 6 5w m 0 0 1 0 2 11 2 1w m 0 4 n o i t a r u g i f n o c d r a d n a t s when placing an order please specify desired shipping: tubes or tape & reel. n o i t a m r o f n i g n i r e d r o t r a p d r a d n a t s e g a k c a p r e b m u n t r a p g n i r e d r o s n i pe l y t sg n i k r a m t r a p 8 2p o s ql t g 0 6 5 c a p 8 2p o s ql t g 1 2 1 c a p
california micro devices ? 2000 california micro devices corp. all rights reserved. 2/00 PACGTL 2 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com recommended layout for socket 370 (option a) for celeron? and mendocino? cpus 11-mil track pitch, single layer note: this option requires 1 metal layer in board routing for all 119 gtl termination lines.
?2000 california micro devices corp. all rights reserved. 2/00 3 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com california micro devices PACGTL recommended layout for socket 370 (option b) for celeron? and mendocino? cpus note: this option requires 2 metal layers in board routing for all 119 gtl termination lines. please note that the second laye r only uses 6 short traces, minimizing potencial interference with other traces, and also minimizing the number of vias.
|
